1. Field of the Invention
This invention relates generally to the field of analog circuit design and, more particularly, to Digital to Analog Converter (DAC) design.
2. Description of the Related Art
Analog-to-digital converters (ADCs) are circuits used to convert signals from the analog domain, where the signals are typically represented by continuous quantities such as voltage and current, to the digital domain, where the signals are generally represented by discrete quantities such as numbers. Similarly, Digital-to-Analog converters (DACs) are circuits used to convert signals from the digital domain to the analog domain. These circuits can be implemented in a variety of ways. Well known and often used conversion techniques include flash, delta-sigma (or sigma-delta), sub-ranging, successive approximation, and integrating.
One often-utilized basic building block of an ADC is the analog integrator, commonly implemented as a switched-capacitor integrator (SCI) 100 illustrated in FIG. 1. Operation of SCI 100 consists of two main phases, the sampling phase and the charge transfer, or integration phase. During the sampling phase an input voltage vi 110 is coupled to a first terminal of input capacitor Cinp 104 through switch P1120, while switch P2122 couples the second terminal of Cinp 104 to ground. Thus Cinp 104 is charged to a voltage level corresponding to vi 110. During the integration phase, P1120 is used to couple the first terminal of Cinp 104 to ground, while P2122 is switched to couple the second terminal of Cinp 104 to the inverting input terminal of operational amplifier (OP-AMP) 102, and to integration capacitor Cint 106. Cint 106 is connected to form a feedback loop between the inverting input and output terminal of OP-AMP 102. Thus, during the integration phase the charge stored across Cinp 104 is transferred to Cinp 106. The ratio Cinp/Cint determines the gain of vo 112 with respect to vi 110.
One example of an ADC (and DAC) is the “delta-sigma converter” or “sigma-delta converter”, which is well known in the art. Use of Delta-sigma (D/S) converters has proliferated due primarily to their capability for high-resolution analog-to-digital conversion in mixed signal VLSI processors. A D/S converter typically digitizes an analog signal at a very high sampling rate (multiple oversampling) in order to perform noise shaping. Digital filtering following the noise shaping allows the D/S converter to achieve a higher resolution than conventional ADCs. Decimation after the filtering reduces the effective sampling rate to the “Nyquist” rate.
FIG. 2 illustrates a block diagram of a single bit D/S converter 10, commonly known in the art. Single bit D/S converter 10 includes a single bit D/S modulator 12 coupled to a digital filter and decimation circuit 14. D/S modulator 12 includes a summing node 16, an integrator 18, a single bit ADC 20, and a single bit DAC 22. DAC 22 is coupled to the output of ADC 20 and provides feedback to summing node 16. An analog input signal Vin is connected to one input (add) of summing node 16, and the output of DAC 22 is connected to another input (subtract) of summing node 16. In operation, the output of summing node 16 is integrated by integrator 18 and subsequently converted into a single bit, digital signal by ADC 20. The single bit digital signal is in turn converted back to an analog signal by DAC 22 and subtracted from analog input signal Vin at summing node 16. Single bit D/S modulator 12 converts Vin into a continuous serial stream of 1s and 0s at a rate determined by a sampling clock frequency, kfs. Due to the feedback provided by DAC 22, the average value output by DAC 22 approaches that of Vin when the gain of the loop is high enough.
FIG. 3 shows a block diagram of a multi-bit D/S converter 50. Multi-bit D/S converter 50 includes a multi-bit D/S modulator 52 coupled to a multi-bit digital filter and decimation circuit 54. Multi-bit D/S modulator 52 further includes a summing node 56, an integrator 58, a multi-bit ADC 60, and a multi-bit internal DAC 62. Multi-bit D/S modulator 50 of FIG. 3 operates similarly to the single-bit D/S converter of FIG. 2. The output of summing node 56 is integrated by integrator 58 and converted into a multi-bit digital signal by multi-bit internal ADC 60 operating at oversampling rate kfs. Multi-bit DAC 62 is connected via a feedback loop between the output of the multi-bit ADC 60 and an input node of the summing node 56, whereby the analog signal output of DAC 62 is subtracted from analog signal input Vin. Again, the output of DAC 62 approaches that of analog input signal Vin as a result of the feedback. Digital filter and decimation circuit 54 removes quantization noise shaped into the higher frequencies and re-samples the over-sampled digital signal at rate fs.
Multi-bit D/S converter 50 of FIG. 3 provides benefits over single bit D/S converter 10 of FIG. 2. Namely, the multi-bit D/S converter 50 provides more resolution and less quantization noise for a given oversampling rate. Additionally, multi-bit D/S converter 50 is more stable than single bit D/S converters. However, multi-bit D/S converter 50 suffers from linearity errors introduced by internal multi-bit DAC 62. Single bit D/S converters on the other hand do not produce linearity errors. Linearity error is due to the inability of the multi-bit DAC to accurately translate a digital input value into an analog current or voltage. In other words, given a particular digital input, the resulting analog output of multi-bit internal DAC 62 approximates the digital value but does not exactly equal the digital value. In reality, the actual analog output differs from the digital input value by an amount equal to the linearity error.
Another type of ADC is the successive approximation register (SAR) converter illustrated in FIG. 4. The conversion technique used by a SAR converter is also referred to as bit-weighing conversion, where typically a comparator 72 is used to compare the applied analog input voltage Vin 80 against the output of an N-bit DAC 76. Using the DAC 76 output as a reference, the final converted (digital) result Dout 86 is approached as a sum of N weighting steps, in which each step corresponds to a single-bit conversion. At the beginning of the conversion process the SAR 74 bits are all initialized to zero. The most significant bit (MSB) of SAR 74 is then set to ‘1’ (or high) and the voltage as represented by SAR 74 (and produced by DAC 76) is compared with Vin 80. A Vin 80 value lower than the voltage represented by SAR 74 would imply that SAR 74 holds too large a value, which has to be reduced, in which case the MSB of SAR 74 is reset to zero. On the other hand, a Vin 80 value higher than the voltage represented by SAR 74 would imply that the register value is not large enough to equal Vin 80, in which case the MSB of SAR 74 is allowed to retain its value of ‘1’. In the next cycle, the next significant bit of SAR 74 is set to ‘1’ and the same process is performed iteratively. As each bit is determined, it is latched into SAR 74 as part of the ADC's output. Typically controlled by a logic control circuit 78 which is operated synchronously through the use of clock signal 82, the aforementioned steps are executed N times for an N-bit ADC, at the end of which the contents of SAR 74 will correspond to the analog input voltage Vin 80 provided to the ADC. The beginning and end of the conversion process may be determined through a set of appropriate control signals.
Generally, single-bit DACs do not exhibit the non-linearity characteristics of multi-bit DACs. Accordingly, ADCs employing a single bit internal DAC do not suffer from linearity errors, and are therefore more accurate. In this respect, single bit internal DACs are preferred over multi-bit internal DACs. However, when utilizing the D/S technique, due to the resolution and stability of a multi-bit D/S converter being superior to that of a single bit D/S converter, it is preferable to use multi-bit D/S converters, where increased accuracy is achieved by removing or reducing the non-linearity produced by the D/S converter's internal multi-bit DAC. Similarly, while SAR converters generally operate at fast speeds and typically feature lower complexity and low power consumption, they are also directly affected by the accuracy of their internal DAC.
One technique used for increasing DAC accuracy has been Dynamic Element Matching (DEM), which cycles through a multiplicity of unit capacitors used in the DAC to cancel out mismatch errors. This technique typically requires a large silicon area because a unit capacitor is needed for each least significant bit (LSB) of the DAC. For example, a five-bit DAC would require 31 separate unit capacitors. Similarly, a 16-bit audio DAC would typically require −65 k unit capacitors. To make an accurate audio DAC, a Delta Sigma architecture is generally used with a multi-bit quantizer using the aforementioned DEM technique.
In other words, one drawback of the DEM technique is that its use is typically restricted to low bit DACs since it requires a unit capacitor for each LSB of the DAC. Present day audio DACs are generally designed using the D/S technique. Though systems with resolutions of up to 24-bits have apparently been achieved using this technique, the linearity of such systems is difficult to verify. The drawback of D/S based design lies in the complexity of the DEM technique itself and the complex analog output filter it typically requires. Previously, capacitor DAC accuracy has been limited to the physical matching obtainable on silicon, which is approximately 0.1% (11 bits).
One proposed solution to the DAC accuracy problem has been the use of a technique of charge redistribution first introduced by Suarez et al in the IEEE publication “All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques—Part II”, IEEE Journal of Solid State Circuits, Vol. SC-10, No. 6, December 1975. The technique involves the use of two small capacitors and some switches to juggle a charge between the two capacitors to form the final DAC voltage. A significant limitation of this technique lies in its susceptibility to a mismatch error between the two capacitors. It also requires more clock cycles to convert the digital word into an analog voltage than other available techniques.
Therefore, there still exists a need for a system and method for designing highly accurate, low power, compact size DACs.